Technical Field
The present disclosure relates to a semiconductor electronic device with improved testing features, during an electrical testing operation, for example in the final steps of a corresponding manufacturing process. The present disclosure further relates to a corresponding packaging method.
Description of the Related Art
The desire is generally felt, in the field of packaging of semiconductor electronic devices, for size reduction, in particular in the field of portable electronic apparatuses, such as smartphones, tablets, phablets, wearable apparatuses, and the like.
Moreover, the recent trend is known to provide, inside a single package, complex electronic systems, to obtain a so-called SiP (System-in-Package), including a number of dies of semiconductor material housed in a same package. The various dies integrate respective integrated circuits including, for example, MEMS (Micro-Electro-Mechanical Systems) structures, analog, digital, or mixed-signal electronic interface circuits (the so-called ASICs—Application-Specific Integrated Circuits), memories, logic processing units, radiofrequency circuits, and the like, generally co-operating with one another to perform one or more desired functions.
The various dies within the package are electrically connected in an appropriate manner to enable exchange of electrical signals, and electrical connection elements are further provided carried by an outer surface of the package, for interfacing with external electronic systems, for example for electrical coupling with a printed circuit board (PCB).
In particular, stacked-packaging solutions are known, envisaging that the various dies are arranged in the package vertically stacked on one another, in order to obtain a smaller horizontal dimension of the package and in general to optimise the resulting size.
For instance, FIG. 1 shows a possible solution of a stacked-die package 1.
In the example illustrated, a first die 2, for example including a MEMS structure is stacked on a second die 3, for example including an ASIC, within the package 1.
The stacked structure constituted by the first and second dies 2, 3 is arranged on a supporting layer 4, constituting the base of the package 1 and having a top surface 4a, which is in contact with the second die 3, and a bottom surface 4b, which is in contact with the environment external to the package 1 and carries appropriate electrical contact elements 5, in the example in the form of lands, designed, for example, for coupling with a printed circuit board (PCB) (likewise, electrically conductive bumps may, instead, be provided).
The direction of stacking of the first and second dies 2, 3 within the package 1 is vertical, i.e., along a vertical axis z orthogonal to the plane of horizontal extension xy of the top and bottom surfaces 4a, 4b of the supporting layer 4.
In particular, the first and second dies 2, 3 each have a respective top surface, which lies parallel to the aforesaid horizontal plane xy, provided on which are respective contact pads 6, electrically connected to the MEMS structures and/or to the electronic circuits integrated in the same dies (as will be evident to a person skilled in the field).
Further contact pads 7 are provided on the top surface 4a of the supporting layer 4, and electrical connection wires 8, according to the so-called wire-bonding technique, electrically connect the electrical contact pads 6 of the first and second dies 2, 3 to the further contact pads 7. Electrical connection between the further contact pads 7 and the electrical contact elements 5 carried by the bottom surface 4b of the supporting layer 4 is provided by through silicon vias 9 that traverse the entire thickness (along the vertical axis z) of the supporting layer 4.
An insulating coating 10, the so-called “mould compound”, made, for example, of epoxy resin, coats the stacked structure of the first and second dies 2, 3, and the outer portions of the top surface 4a of the supporting layer 4 not covered by the second die 3. A top surface 10a of the insulating coating 10 constitutes an outer surface of the entire package 1, in contact with the external environment.
The solution described, although providing in a compact manner electrical coupling between the first and second dies 2, 3 and between the same dies 2, 3 and the external environment, has, however, a limitation due to the dimensions of the stacked dies, which decrease in the horizontal plane xy as the distance along the vertical axis z from the front surface 4a of the supporting layer 4 increases. In fact, as is evident from an examination of FIG. 1, the dies that are vertically stacked on one another have an “encumbrance” in the horizontal plane xy that progressively decreases starting from the top surface 4a of the supporting layer 4. Moreover, the same dies have a different size in the horizontal plane xy.
There follows an upper limit to the number of dies that may be stacked vertically inside the package 1, a limit that may not be acceptable, at least in certain applications, and further constitutes a limitation to optimal exploitation of the space inside the package 1.
A further solution that has been proposed to overcome the above limitations is illustrated in FIG. 2.
In this case, the dies inside the package 1 are vertically stacked on one another, aligned along the vertical axis z, and have substantially the same encumbrance in the horizontal plane xy. In particular, FIG. 2 illustrates, by way of example, three dies, a first die and a second die, once again designated by 2 and 3, and also a third die 13.
As is known, and as illustrated schematically, each die 2, 3, 13 comprises a respective substrate 2a, 3a, 13a of semiconductor material, for example silicon, provided in which, with known techniques (not described in detail herein) is an appropriate integrated circuit, including, for example, digital, analog, or mixed-signal electronic circuits, memories, logic processing units, radiofrequency circuits, MEMS structures, etc.
Each die 2, 3, 13 further comprises, above the substrate, a multi-layer 2b, 3b, 13b constituted by the superposition of a number of metallization layers, connected together by through vias, and interposed dielectric layers. The aforesaid electronic circuit may be formed, at least in part, also within the multi-layer 2b, 3b, 13b; for example, a gate-oxide region of a MOS transistor may be defined in a first insulating layer of this multi-layer, and a corresponding gate region in a first conductive layer thereof.
Suitable electrical paths (not illustrated herein) are provided within the multi-layer 2b, 3b, 13b designed to transfer electrical signals between the integrated electronic circuit and respective contact pads 6, which are provided at least in part in a top metallization layer of the multi-layer 2b, 3b, 13b and are arranged on the top surface of the respective dies 2, 3, 13.
In this case, the electrical connection between the dies 2, 3, 13 is provided by respective internal through silicon vias (TSVs) 11, which traverse the entire thickness (along the vertical axis z) of the substrate 2a, 3a, 13a of each die 2, 3, 13, electrically coupling to the pads 6 of the underlying die in the stack and reaching a top surface of the same substrate 2a, 3a, 13a. In the case of the first die 2, the internal through silicon vias 11 are electrically coupled (by appropriate connection paths, not illustrated) to the through silicon vias 9 provided through the supporting layer 4, so that the electrical signals are transported from the stacked structure of the dies 2, 3, 13 towards the electrical connection elements 5 on the outside of the package 1.
Although advantageous, in so far as it enables a further reduction of the horizontal dimensions of the package and does not have limitations to the vertical stacking of a desired number of dies, also this solution has a number of drawbacks.
In particular, during electrical testing, performed, for example, at the end of the manufacturing process, this solution does not in general enable access to the contact pads 6 of the dies (in the example, the dies 2 and 3) arranged inside the stacked structure, in so far as they are covered by overlying dies; basically, there are portions of the resulting stacked structure that may not be reached and are not observable, and thus may not be tested.
As it is clear, this problem is accentuated when two or more dies, as in the example illustrated in FIG. 2, have the same or comparable encumbrance in the horizontal plane xy.
Accordingly, there may be situations in which electrical testing does not enable identification of malfunctioning of the resulting electronic device, or else determination of the origin of any found malfunctioning, or in any case does not allow to show that the desired performance has been achieved.